Computer monitoring system

ABSTRACT

There is disclosed a computer monitoring system for detecting, filtering and storing &#39;&#39;&#39;&#39;hardware events&#39;&#39;&#39;&#39; and &#39;&#39;&#39;&#39;software events&#39;&#39;&#39;&#39;. Hardware events are counted or timed, while software events resulting from special store instructions are selectively stored in a monitor memory. Software events can be used to initiate or terminate hardware measurements. Both hardware and software events may be stored exhaustively or only the most recent of a fixed number of events can be stored. Storage takes place on a plurality of tape units for later analysis.

United States Patent 1 1 Martin COMPUTER MONITORING SYSTEM {75] Inventor: Robert Lanham Martin,

Greensboro, NC.

[73] Assignee: Bell Telephone Laboratories Incorporated, Murray Hill, NJ.

[22] Filed: May 18, I973 [21] Appl. No: 361,559

14 1 Sept. 16, 1975 ll/I973 Ling 340N725 ll/I973 Bclady 340/1725 OTHER PUBLICATIONS Program Monitoring Technique." IBM. Technical Disclosure Bulletin, H. W. Flanagan, Vol. [3. No. 8.

January 1971, pp. 2399-2401.

Primary Examiner-Gareth D. Shaw Assistant Examinerlames D. Thomas Attorney, Agent or Fl'rmR. O. Nimtz [52] US. Cl. 340/1725; 235/153 AC [51 Int. Cl. G06F 11/00; GO6F I H06 [57] ABSTRACT [58] Fleld Search 340/1725; 235/153 There is disclosed a computer monitoring system for 235/153 AK detecting, filtering and storing hardware events" and software events. Hardware events are counted or [56] References Cned timed, while software events resulting from special UNITED STATES PATENTS store instructions are selectively stored in a monitor 3,509541 4 1970 Gordon 340/1725 memory Software events can be used to initiate or 1522597 8/1970 Murphy. 340/1725 terminate hardware measurements. Both hardware .54 11/1 M rphy- 340/172 and software events may be stored exhaustively or 1 wirsing-- 340/|72-5 only the most recent of a fixed number of events can be stored. Storage takes place on a plurality of tape e aog r I ts f l t l 1696.340 10/1972 Matsushita. 340/1725 um or der 3761474 10/1973 Freeman 340/1725 7 Claims, 37 Drawing Figures COMPUTER MONITOR PRIOR ART L COMPUTER 1 HARDWARE SOFTWARE EVENTS EVENTS N2 INTERFACE BUFFER UNIT ll l3 lNlTlA MATCHER -44 ICIZATION LOGC 16 SECTION m1 1 COUNTER STORE T LIZATION CONTROL CONTROL INITIALIZATION 19 FILTERS FILTERS l7 l8 INITIALIZATION COUNTERS INITIALIZATION TAPE UNITS PATENTED Q E 3806,4554

SHEET 1 FIG. COMPUTER MONTTOR PRIoR ART COMPUTER I0 HARDWARE soFTwARE EVENTS EVENTS "/42 INTERFACE BUFFER UNIT l3 MATCHER NITIAICIzATIoN LOG'C I6 SECTION COUNTER sToRE INITIAIiIZATION CONTROL CONTROL INITIALEIZATION I9 FILTERS FILTERS I7 I8) {I5 INITIALIZATION COUNTERS 27 CONTROL 28 LOGIC 20 2 INITIALIZYATION sToRE INPUT cIRcUITs sToRE I CONTROL sToRE cIRcUITs TAPE CONTROLLER TAPE UNITS PATENTED SEP I 61975 SHEET 2 WE CB| FIG. 2A

\ T cs2 lNPUT DATA wORD FORMAT EVENT BITSHZ) (NOT USED) DATA(32) FIG. 28 we OUTPUT DATA wORD FORMAT UNIT 10(5) EVENT ensue) TlME-OF-DAY BITS(I4) DATA(32) FIG. 2C wB TIME OF DAY wORD FORMAT DATA UNTT ID 5 STATUSUB) Loam) TIME OF DAYU3MSB) TlME-OF-DAY(32LSB) FIG. 20 we sTATUs wORD FORMAT UNIT 113(5) STATUS BITS(26) TI ME- OFDAY(32) UNIT ID(5) MODETS] COUNT BITS(20) WORD A WORD B WORD A WORD B WORD A WORD B WORD A WORD B WORD A PATENTED SEP 1 6 I975 SEIEET 5 F/G.8 INTERFACE BUFFER UNIT (REQUESTS 5O 58- SYNC PRIORITY DATA INPUT TIME OF DAY cIRcUITs cIRcUTs GENERATOR U4) DATA A TIME LOST DATA CONVERGENCE CIRCUITS TO MATCHER 56 l54 I LOGIC sEcTIoN (FIcIsI LOST DATA (5) UNIT ID (5) IDATA(A+B) TOD c451 To STORE INPUT cITcUITs F/G.2.3 SOllON OFF ADVANCE coUNTER cIRcUITs S C 504 505 (I6 REQD) ON/ FF INITIALIzATIoN -sI2 coUNTER COUNT SELECTION CLEAR I (2o) REGlSTER READ[- GATE --5oa SIO;

507 cDUNT COUNT COMPARE COMPARE COUNT REGISTER 509 5|5 5|6 2" DETECTED SELECT an E GATE DETEcTDR COUNTS TO GRAY'TO- BINARY CONVERTER (F1620) PATENTED SEP I SIQTS 5. 906,454

EIEF'I 6 FIG. 9

PRIORITY AND LOST DATA cIRcuITs REOuEsTs IITI 1 I HOLD CLEAR CLEAR LOST DATA REGIsTER ITI I) TEsT DELAY REGISTER I I41 I40 I22 GATE (To) I42 GATE DATA DATA DET DET CLEAR SNAP-SHOT LEAR LOST DATA REGISTER Tu (TH) REGISTER U23 I30 I43 ENABLE (T6) I24 COMPETITION GATE -|44 cIRcuIT (T6) I34 I45 PRIORITY (Tl) LOST CLEAR REGISTER R33 DATA cOuNTER MEMORY GATE -I2G REsuIYIE) GATE T I I IA I N G TDD REO GENERATOR To MEM IaI LOST DATA UNIT 10 GENERATOR TIO) Q' E E (TIG) 5R8; IA TO INPUT AND TIMING TO STORE CONVERGENCE CIRCUIT PULSES INPUT CIRCUITS (FIG. (FIG. 24)

PATENTEI] SEF I 6 I875 iliiEI 'I TO II HO n PRIORITY TIMING TII n I I I I I I L IO I5 TIME (ARI UNITS) FIG. INPUT AND GONvERGENcE CIRCJITS 0- DATA NlTOD (BITS 0-13) I63 I INPUT STROBE (HOLD FULL) DATA INPUT GATE CLEAR DATA INPUT /l64 TIME S/Ies (T I I I REGISTER RI GISTER OUTPUT STROBE 5' GATE M167 (T6) gm V -T69 CLEAR DATA OUTPUT OUTPUT TIME (TI) REGISTER REGISTER PARITY V173 CHECKER UNIT ID. (5) TO MATCHER (FROM FIG.9)

SECTION .I TO STATUS TO STORE INPUT REGISTER I; IRCU ITS FIG. 24)

PATENTED SEP I 81975 F' CD SHEET 9 FIG. /.3

MATCHER LOGIC SECTION (B REO'D) mm ID EVENT ID DATA ODD VALUE VALUE VALuE WW 2I5 3,, 2|9 223 227-1229 (239 '2 UNIT E EVENT E DATA 6 L.J-'MATCHER fir. LOGICAL LOGICAL ARITHMETIC :5 OuTPuT gig COMPARE COMPARE COMPARE P-REGISTER :0 g 22I 225 233 3| 237 235 um ID EVENT ID DATA T MAsR MASK MASK 2I3 uNIT 10(5) EVENT 1on4) DATA(32) SOFTWARE EVENT 2 DATAwORD uNIT ID EVENT ID DATA ,m

MASK MASK MASK 2 0 1222 226 23B ,240 3 uNIT EVENT A MATCHER w LOGICAL T: LOGICAL E ARITHMETIC OuTPuT -jg COMPARE COMPARE COMPARE REGISTER 12: 220 224 22B 230 232 UNIT ID EVENT ID DATA Y VALUE VALuE VALuE B YF 2l8 2I6 PATENTEDSEP I 61975 3. 906.454

SHEEI 11 FIG. /5 DATA COMPARE CIRCUIT FIRST LEVEL (6) SECOND LEVEL (I) PATENTEUSEF I SIQTS 3, 906,454

SHEET 1? FIG. /6

BASIC FILTER l CLEAR I g 334 s C FILTER B CONTROL REGISTER O (FCR) 6 O B 333 FROM E MATCHER I (FIG.I3) 6 335 COMPARE GATES FIG. 7

I N IT COUNTER CONTROL 1 FILTE'R I I I I (8 REG D) ON OFF INCR READ 358 FCFI FCR FCR FCR MATCHER OUTPUT I 35 5; A 352 L353 (F|G.l3) I I I I ON OFF INCR READ COMPARE COMPARE COMPARE COMPARE 360 1 364 1 355 1 356 1 361 GATE 56%? 4 4 4 359 STROBE 36I ON 362 OFF 363 INCR 364 READ FIG. 18

IN IT sTORE CONTROL Fl LTEIR I I I I I4 REQD) ENABLE DISABLE INCLUDE EXCLUDE FCR FCR FCR FCR MATCHER OuTPuT 3TO 3TI 372 IFI6.I3I I I I I ENABLE DIsABLE INCLUDE ExCLuDE COMPARE COMPARE COMPARE COMPARE 380 @374 I 376 1 376 1 \377 GATE FILTER OuTPuT STROBE IENABLE iDlSABLE INCLUDE lEXCLUDE PATENTEI] SEF I 6 I975 SHEET FIG. 20

COUNTER SECTION INITIALIZATION HARDWARE IMHZZOMHZ FROM INITIALIZATION EVENTS MATCHER (232) 436 SECTION (GLEB) COUNTER CONTROL 433 FILTERS COUNTER -434 EVENT SELECTION SELECTION REGISTER REGISTER INCR(8);

COUNTER INPUT SWITCHES (I6) 430 COUNTERS ON,OFF, READ 443- a) UNIT I.D. GRAY-TO-BINARY MODE GENERATOR CONVERTER ENCODER ID. COUNT OUTPUT MODE REGISTER REGISTER REGISTER (5) (20 (6) 44G-| UNIT 1.0. COUNT MODE V TO STORE INPUT CIRCUITS (FIG. 24) 

1. A computer monitor system comprising a software event selection circuit responsive to programmed event signals and preselected constant signals for selecting one of a plurality of received software event signals, a hardware event counting circuit responsive to hardware event signals for counting selected ones of said hardware event signals, and a counter control circuit responsive to said software event selection circuit for enabling, disabling, incrementing, or storing the output of said hardware event counting circuit, said software event selection circuit including a plurality of matching circuits for matching source identification signals, event identification signals and event value signals with respective preselected constant signals for each said programmed event signal.
 2. The computer monitor system according to claim 1 wherein said hardware event counting circuit includes a plurality of counters, an input selection matrix, a plurality of constant signal registers, said matrix being responsive to counter selection constant signals in said registers and mode selection constant signals in said registers to connect selected event signals to selected counters in said counting circuit.
 3. The computer monitor system according to claim 1 further including a data storage circuit, and means for storing in said storage circuit only selected software event signals and only selected hardware event count signals from said counting circuit.
 4. The computer monitor according to claim 3 wherein said data storage circuit comprises a Magnetic core memory, and a plurality of magnetic tape units, and means for accumulating said selected software and hardware event count signals in fixed-size blocks in said magnetic core memory before transfer to said tape units.
 5. The computer monitor according to claim 4 further including means for cyclically storing the most recent of said selected event signals in excess of the capacity of a preselected portion of said magnetic core memory in place of the earliest stored event signals in said magnetic core memory.
 6. A computer monitoring system for selecting only a portion of a plurality of software event data signals reflecting the operation of said computer, said monitoring system comprising a plurality of matching signal registers for storing preselected constant signals to be used for comparisons with portions of said data signals, an equal plurality of comparison circuits for comparing said constant signals to said portions of said data signals, and a storage register for storing only those of said data signals for which all of said comparison circuits indicate preselected relationships between said constant signals and all of the respective portions of each of said data signals.
 7. A computer monitoring system comprising a software event selection circuit responsive to programmed event signals and preselected constant signals for selecting one of a plurality of received software event signals, said selection circuit including a source identification signal matching circuit for comparing a source identification signal with a first preselected constant signal, an event identification signal matching circuit for comparing an event identification signal with a second preselected constant signal, and an event value signal matching circuit for comparing an event value signal with a third preselected constant signal. 